The present invention relates to a method for making semiconductor devices, particularly those that include a dual damascene interconnect.
Dual damascene interconnects may enable reliable low cost production of high speed semiconductor devices that have gate lengths of 0.18 micron or less. A conventional process for making devices that include such an interconnect includes the following steps. A first barrier layer, e.g., one containing silicon nitride, is formed on a substrate to prevent copper from diffusing into a dielectric layer, which is subsequently deposited onto the barrier layer. A via and trench are then etched into the dielectric layer. A second barrier layer, e.g., a metal based layer, is formed to line the via and trench, followed by filling the via and trench with copper. This metal based barrier layer prevents copper from diffusing into the dielectric layer. After applying a chemical mechanical polishing (xe2x80x9cCMPxe2x80x9d) step to remove copper from the surface of the dielectric layer, the process is repeated with a diffusion barrier layer being deposited on the copper and the dielectric layer, followed by forming another dielectric layer on top of that barrier layer, and so on.
When certain low-k materials are used to form the dielectric layer, these conventional dual damascene processes may require a hard mask to be formed on the dielectric layer to protect it when the trench and via are formed. In addition, separate photoresist patterning and etching sequences are required to create the via and trench. Such extra process steps increase process complexity and cost.
Accordingly, there is a need for a less complicated and less expensive process for making a semiconductor device that includes a dual damascene interconnect. There is a need for such a process that forms such an interconnect within a low-k dielectric material. The present invention provides such a process.